Conventional counter-based lock detectors function by comparing a reference clock and voltage-controlled oscillator (VCO) feedback clock within a specified period of time according to a locking accuracy specification. Conventional lock detectors usually need to count thousands of clock cycles to achieve the locking accuracy. However, during the initial process of phase locking for a phase-locked loop (PLL), the VCO frequency can be much higher or lower than the reference frequency. A difference between the VCO frequency and the reference frequency can produce an unlock signal even if the PLL is already in lock at the end of a first lock detection window. A second lock detection window needs to be started and additional thousands of clock cycles are wasted for comparison. Even if the first detection window succeeds to produce a correct output, the PLL still needs a long time for the specified accuracy. In many applications, such as in a memory interface, only a few hundred clock cycles are allowed to be used for lock detection.
It would be desirable to implement a fast-response hybrid lock detector.